The present invention relates to a sensing circuit for serial dichotomic sensing of multiple-levels non-volatile memory cells.
The market demand for non-volatile memories with higher and higher storage capacity is forcing the semiconductor manufacturers to a continuous effort in scaling the devices and in increasing the chip size.
As an additional possibility to increase the memories"" capacities, it has been proposed to store more than one bit per memory cell: a memory device with memory cells capable of storing two or even four bits has a storage capacity two or, respectively, four times higher than that of a memory device with the same chip size but with memory cells capable of storing only one bit each.
Non-volatile memory cells (i.e., memory cells which retain their programming state even in the absence of power) are generally represented by MOS field-effect transistors; data can be programmed in non-volatile memory cells by changing the threshold voltage of the MOS field-effect transistors: in the case of ROMs this is done during their fabrication, while in the case of EPROMs, EEPROMs and Flash EEPROMs, the change in the threshold voltage is achieved by properly biasing the MOS field effect transistors to cause an injection of charges in a floating gate.
To determine the programming state of a non-volatile memory cell, i.e., to xe2x80x9creadxe2x80x9d or to xe2x80x9csensexe2x80x9d the contents of the memory cell, a fixed voltage VG is applied to the control gate of the MOS transistor: the programming state of the memory cell can thus be determined by detecting the position of the threshold voltage of the MOS transistor with respect to said fixed gate voltage.
In the most common case of non-volatile memory cells that are capable of storing only one bit of information, a memory cell can show two different programming states (logic levels), corresponding to two different threshold voltage values; hereinafter, such a cell will be called a xe2x80x9ctwo-level memory cell.xe2x80x9d The reading of the memory cells is performed by a so-called xe2x80x9csensing circuit,xe2x80x9d which delivers a voltage signal having two distinct possible values, corresponding to the two logic levels.
In the case of non-volatile memory cells that are capable of storing more than one bit of information, a memory cell must be able to show m=2n distinct programming states or levels, where n represents the number of bits which can be stored in the memory cell; in the following, such a cell will be called a xe2x80x9cmultiple-level memory cell.xe2x80x9d As in the case of two-level cells, each level corresponds to a different value for the threshold voltage of the MOS transistor.
The discrimination of the m different programming levels can be performed by means of a either a voltage-mode sensing technique or a current-mode sensing technique. In the latter case, for example, the allowed threshold voltage range of the memory cell is divided, on the basis of the electric and physical characteristics of the memory cells, into m sub-intervals, each corresponding to one of the different m levels to be discriminated. The memory cell is then programmed in a desired one of the m different levels by properly adjusting its threshold voltage, so that when the memory cell is biased in the prescribed sensing conditions, it sinks a current corresponding to the desired programming level.
Two sensing techniques have been proposed for multiple-level memory cells: parallel-mode sensing and serial-mode sensing.
Parallel-mode sensing is for example described in A. Bleiker, H. Melchior, xe2x80x9cA Four-State EEPROM Using Floating-Gate Memory Cells,xe2x80x9d IEEE Journal of Solid State Circuits, vol. SC-22, No. 3, July 1987, pp. 460-463. This technique is the natural extension of the conventional technique used for two-level memory cells, and provides for generating mxe2x88x921 distinct predetermined references (current references for the current-mode approach, or voltage references for the voltage-mode approach), and for performing mxe2x88x921 simultaneous comparisons of such mxe2x88x921 distinct voltage or current references with a current (or a voltage) derived from the memory cell to be read.
The advantages of the parallel-mode sensing technique are its high speed and the independence of the sensing time from the programming state of the memory cell; a disadvantage is the large area required by the sensing circuit, since mxe2x88x921 distinct comparison circuits are necessary to perform the mxe2x88x921 simultaneous comparisons.
Differently from parallel-mode sensing serial-mode sensing requires just one reference (current or voltage), which can be varied according to a prescribed law. This single reference is used to perform a series of successive comparisons, and is varied to approximate the analog current or voltage derived from the memory cell to be read. A serial-mode sensing circuit is simple to implement, and requires only a small area.
Two different kinds of serial-mode sensing methodologies are known, which differ in the law according to which the reference is made to vary.
The first methodology, also called xe2x80x9csequential,xe2x80x9d described for example in M. Horiguchi et at., xe2x80x9cAn Experimental Large-Capacity Semiconductor File Memory Using 16-Levels/Cell Storage,xe2x80x9d IEEE Journal of Solid State Circuits, vol. SC-23, No. 1, February 1988, pp. 27-32, consists of a succession of comparisons (at most mxe2x88x921 ) between a fixed quantity (voltage or current) and a variable quantity (voltage or current) which is sequentially varied starting from an initial value.
For example, the fixed quantity can be the current sunk by the memory cell to be read (subject to a prescribed biasing condition), while the variable quantity can be a current supplied by a digitally-driven generator. The (constant) current sunk by the memory cell to be read is compared with a reference current which takes successively increasing (or decreasing) discrete values starting from a minimum (or maximum) value; said discrete values are ideally chosen in such a way as to fall between the different current values corresponding to the m programming levels of the memory cell, so that the result of a comparison is negative (or positive) as long as the reference current is lower (or higher) than the cell""s current. The series of successive comparisons stops after the first positive (or negative) result; the last value of the reference current represents the current of the memory cell, except for a constant term associated with the position of the reference current value with respect to the programming levels of the memory cell.
It appears that the time required to read a memory cell with the serial sequential method is not uniform, but depends on the particular programming level of the memory cell and on the starting value of the reference voltage or current (the sensing time depends on the distance between the programming level of the cell to be read and the starting value of the reference voltage or current): from a minimum of one to a maximum of mxe2x88x921 comparison steps are necessary to determine the programming state of an m-level memory cell. The sensing time soon becomes excessive with an increase in the number of bits stored in a single memory cell.
The second serial-mode sensing methodology, also called xe2x80x9cdichotomic,xe2x80x9d is described in the co-pending European Patent Application No. 95830023.8 filed on January 27, 1995 in the name of the same applicant. This methodology consists of a successive approximations search that, starting from an initial value for the reference current, finds the value of the memory cell current after a succession of iterations. At each step of the iterative search, the (constant) memory cell current is compared with the variable reference current, whose value is chosen according to a dichotomic or xe2x80x9cbinary searchxe2x80x9d algorithm. The initial interval of possible memory cell current values is divided in two parts: depending on the result of the comparison, the successive dichotomy will be applied to only that part of the initial interval wherein the memory cell current falls; the iterative search is recursively repeated until the value of the memory cell current is determined.
Using the serial dichotomic method, the programming state of a memory cell with m=2n different programming levels is determined in n comparison steps, independently from the particular programing state of the memory cell.
In EPA 95830023.8, a sensing circuit suitable for actuating the serial dichotomic method is also described. The sensing circuit comprises a variable reference current generator controlled by a successive approximation register supplied with an output signal of a current comparator; the successive approximation register comprises a sequential network that, starting from a predetermined initial state, evolves through a succession of states, each one corresponding to one step of the serial dichotomic search.
The circuit implementation of the sensing circuit strongly depends on the structure of the variable reference current generator: this in fact affects the structure of the current comparator and of the successive approximation register.
According to the implementation described in EPA 905830023.8, the variable reference current generator comprises mxe2x88x921 distinct current generators which are activated in a mutually exclusive way; each one of the mxe2x88x921 current generator corresponds to one of mxe2x88x921 values which can be taken by the reference current (absolute current generators technique).
In practice, each current generator is formed by a reference memory cell identical to the memory cell to be read. The reference memory cells are programmed in mxe2x88x921 distinct states which, however, do not coincide with any of the m programming levels of the memory cells to be read, since the reference current values shall fall between the cell current values; in this case, the current comparator can be balanced (i.e., the currents to be compared are supplied to the inputs of the comparator in a 1:1 ratio).
Due to the fact that the reference memory cells are not programmed at the same levels as the memory cells to be read, there is not a perfect equivalence between the circuit branch containing the reference memory cells and the circuit branch containing the memory cell to be read. This means that there is a poor tracking between these two circuit branches with respect to process of biasing condition variations.
As an alternative, if the current comparator is properly unbalanced (i.e., if the currents to be compared are supplied to the inverting and non-inverting inputs of the comparator in a ratio equal to f different from 1, e.g., f=0.7) the reference memory cells can be programmed in mxe2x88x921 distinct programming levels which coincide with the programming levels of the memory cell to be read.
Thanks to this, there is a substantially perfect equivalence between the circuit branch containing the memory cell to be read and the circuit branch containing the reference memory cell; also, every possible variation in process parameters or biasing conditions between the memory cell to be read and the reference memory cell is treated by the comparator as a common-mode contribution.
The drawbacks of having an unbalanced current comparator are that the values of the reference current do not fall exactly in the middle of each interval between successive memory cell current values; in fact, the ratio f causes a linear reduction of the current values. Moreover, in an unbalanced comparator, it is more critical to control the switching characteristics than it is in a balanced comparator.
In view of the state of the prior art described, it is an object of the present invention to provide a sensing circuit for the serial dichotomic sensing of multiple-level non-volatile memory cells that overcome the above-mentioned drawbacks.
According to the present invention, said object is achieved by means of a sensing circuit for the serial dichotomic sensing of multiple-level memory cells that can take one programming level among a plurality of m=2n (n greater than =2) different programming levels, comprising biasing means for biasing a memory cell to be sensed in a predetermined condition, so that the memory cell sinks a cell current with a value belonging to a plurality of m distinct cell current values, each cell current value corresponding to one of said programming levels, a current comparator for comparing the cell current with a reference current generated by a variable reference current generator, and a successive approximation register supplied with an output signal of the current comparator and controlling the variable reference current generator, characterized in that the variable reference current generator comprises an offset current generator permanently coupled to the current comparator, and mxe2x88x922 distinct current generators, independently activatable by the successive approximation register, each one generating a current equal to a respective one of said plurality of cell current values.
In a sensing circuit according to the present invention, the reference current is given by the sum of an offset current plus a current equal to one of the possible values of the memory cell current. By properly adjusting the value of the offset current, it is possible to have reference current values which are exactly central between adjacent memory cell current values. This allows the use of a balanced current comparator, which is advantageous with respect to an unbalanced one.